Profile

Profile

  • Name: Tomoya Nagatani (t-ngtn)
  • Affiliation: The University of Tokyo
  • Major: Computer Science
    • FPGA Development
    • High-Level Synthesis
    • Hardware Security

Skill

  • Programming Languages
    • Go
    • TypeScript(React/Next.js)
    • C/C++
    • Python
    • Verilog/SystemVerilog
  • Fields
    • FPGA Development
      • High-Level Synthesis
    • Web Development
      • Frontend
        • React
        • Next.js
      • Backend
        • Go
        • Python (Django/FastAPI)
      • Infrastructure
        • AWS
        • PostgreSQL / MySQL
    • Management
      • Project Management
        • Agile/Scrum
      • Personnel Management
        • HR

Research

  • Daichi Tokuda, Tatsuya Kubo, Ismail Emir Yuksel, Ataberk Olgun, Haocong Luo, Tomoya Nagatani, Geraldo Francisco De Oliveira Junior, Abdullah Giray Yağlıkçı, Mohammad Sadrosadati, Onur Mutlu, and Shinya Takamaeda-Yamazaki, “Clutch: High Performance Vector-Scalar Comparison using DRAM via Chunked Temporal Coding”, ACM International Conference on Supercomputing 2026 (ICS 2026), July 2026.
  • 久保 龍哉, 篤田 大知, 長谷 知弥, 薄井 真之, Lei Qu, Ting Cao, 高前田 伸也, “大規模言語モデルのための実機In-DRAM計算による低ビット行列積高速化”, 情報処理学会研究会報告2025-ARC-262, No.26, pp.1-9, 於 サンポートホール高松, 2025年8月5日.
  • 篤田 大知, 久保 龍哉, Ismail Emir Yuksel, 長谷 知弥, Ataberk Olgun, Haocong Luo, Geraldo Francisco de Oliveira Junior, Onur Mutlu, 高前田 伸也, “標準DRAMを用いたベクトル-スカラ比較演算のアナログ高速計算手法”, 情報処理学会研究会報告2025-ARC-261, No.10, pp.1-13, 於 猪苗代観光ホテル, 2025年6月9日.
  • Tatsuya Kubo, Daichi Tokuda, Tomoya Nagatani, Masayuki Usui, Lei Qu, Ting Cao, and Shinya Takamaeda-Yamazaki, “MVDRAM: Enabling GeMV Execution in Unmodified DRAM for Low-Bit LLM Acceleration”, arXiv:2503.23817, March 2025.
  • Tatsuya Kubo, Masayuki Usui, Tomoya Nagatani, Daichi Tokuda, Lei Qu, Ting Cao, and Shinya Takamaeda-Yamazaki, “Bulk Bitwise Accumulation in Commercial DRAM”, NeurIPS 2024 Workshop Machine Learning with new Compute Paradigms (MLNCP 2024), December 2024.
  • Tomoya Nagatani and Shinya Takamaeda-Yamazaki, “Development of High-Level Synthesis Compiler Automatically Synthesizing Memory Integrity Verification Engines”, The 6th cross-disciplinary Workshop on Computing Systems, Infrastructures, and Programming (xSIG 2024), August 2024.
  • 長谷 知弥, “メモリ整合性検証機構を有するハードウェア高位合成”, フォレストワークショップ2024, 於 TKPガーデンシティPREMIUM札幌大通, 2024年3月30日.